Abstract
The field programmable gate array (FPGA) is a promising technology for increasing computation performance by providing for the design of custom chips through programmable logic blocks. This technology was used to implement and test a hardware random number generator (RNG) versus four software algorithms. The custom hardware consists of a sun SBus-based board (EVC) which has been designed around a Xilinx FPGA. A timing analysis indicates the Sun/EVC hardware generator computes 1 multiplied by 10 6 random numbers approximately 50 times faster than the multiplicative congruential algorithm. The hardware and software RNGs were also compare using a Monte Carlo photon transport algorithm. For this comparison the Sun/EVC generator produces a performance increase of approximately 2.0 versus the software generators. This comparison is based upon 1 multiplied by 10 5 photon histories.
Original language | English (US) |
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Title of host publication | Proceedings of SPIE - The International Society for Optical Engineering |
Editors | John Schewel, Peter M. Athanas, V.Michael Jr. Bove, John Watson |
Pages | 295-299 |
Number of pages | 5 |
Volume | 2914 |
State | Published - Dec 1 1996 |
Event | High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic - Boston, MA, USA Duration: Nov 20 1996 → Nov 21 1996 |
Other
Other | High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic |
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City | Boston, MA, USA |
Period | 11/20/96 → 11/21/96 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering